Time-predictable Control Systems

The proposed project targets computer based control systems such as robot control systems, factory automation systems, and fly-by-wire systems in airplanes. One common aspect of such systems is that at least some fraction of the functionality must be time-predictable in order to guarantee real-time requirements.

At a first glance such a control system is similar to a general-purpose computer; but the real-time aspect sets requirements that can be very difficult to satisfy with such general-purpose computers. General-purpose computers are designed with a focus on making the average-case fast -- speed is convenience. Unfortunately this has lead to architectures that are hard to analyze, and where the guarantees that can be given on the worst-case execution time (WCET) of a piece of software are quite poor. Several international projects as well as T-CREST and RTEMP have addressed this problem and developed novel time-predictable computers.

From the application programmers perspective a multitude of programming and communication paradigms are used. Different fields, such as robotics, automotive, factory automation, etc., have different traditions, and often the specific brand of a component or subsystem implies the use of specific communication paradigms and protocols.

The aim of the proposed project is to combine the expertise of the Drone Research Laboratory at AAU in guidance and navigation of drones, and in obstacle detection and avoidance systems with the expertise of DTU Compute on time-predictable multicore processors and programming of multicore processors. Within the project we will address the integration of flight control algorithms on drones. Sky-Watch uses such an integrated flight control system in their drones, and the company is investigating means to reduce size and increase performance and flexibility.

The research will focus on programming control systems on multicores by selecting the best models of communication. Two PhD students, one at each University, will address this from the application programmer side and from the computer platform developer side. Four faculty members and the chief development officer from Sky-Watch will be involved in guiding and leading this work.

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Journal Articles


  1. Morten B. Petersen, Anthon V. Riber, Simon T. Andersen, and Martin Schoeberl. Time-predictable Distributed Shared On-Chip Memory.
    Microprocessors and Microsystems, 2019. (doi, pdf)

  2. Emad Jacob Maroun, Henrik Enggaard Hansen, Andreas Toftegaard Kristensen, and Martin Schoeberl. Time-predictable synchronization support with a shared scratchpad memory.
    Microprocessors and Microsystems, 64:34-42, 2019. (doi, pdf)

Reviewed Conference and Workshop Papers


  1. Martin Schoeberl. Multicore Models of Communication for Cyber-Physical Systems.
    Model-Based Design of Cyber Physical Systems (CyPhy'19), October, 2019. (pdf)

  2. Martin Schoeberl, Luca Pezzarossa, and Jens Sparsø. S4NOC: a Minimalistic Network-on-Chip for Real-Time Multicores.
    Proceedings of the 12th International Workshop on Network on Chip Architectures, 8:1-8:6, October, 2019. (doi, pdf)

  3. Martin Schoeberl, Luca Pezzarossa, and Jens Sparsø. A Minimal Network Interface for a Simple Network-on-Chip.
    Architecture of Computing Systems - ARCS 2019, 295-307, May, 2019. (pdf)

  4. Oktay Baris, Shibarchi Majumder, Torur Biskopstø Strøm, Anders la Cour-Harbo, Jens Sparsø, Thomas Bak, and Martin Schoeberl. Demonstration of a Time-predictable Flight Controller on a Multicore Processor.
    Proceedings of the 22nd IEEE International Symposium on Real-time Computing (ISORC), 95-96, May, 2019. (doi, pdf)

  5. Martin Schoeberl, Torur Biskopstø Strøm, Oktay Baris, and Jens Spars\o{}. Scratchpad Memories with Ownership.
    2019 Design, Automation and Test in Europe Conference Exhibition (DATE), 1216-1221, March, 2019. (doi, pdf)


  1. Morten B. Petersen, Anthon V. Riber, Simon T. Andersen, and Martin Schoeberl. Time-Predictable Distributed Shared Memory for Multi-Core Processors.
    2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 1-7, October, 2018. (doi, pdf)

  2. Martin Schoeberl. One-Way Shared Memory.
    2018 Design, Automation and Test in Europe Conference Exhibition (DATE), 269-272, March, 2018. (doi, pdf)


  1. Martin Schoeberl and Jens Sparsø. Timing Organization of a Real-Time Multicore Processor.
    2017 New Generation of CAS (NGCAS), 89-92, September, 2017. (doi, pdf)

  2. Martin Schoeberl, Bekim Cilku, Daniel Prokesch, and Peter Puschner. Best Practice for Caching of Single-Path Code.
    17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017), 1-12, 2017. (doi, pdf)